邏輯電路設(shè)計(jì)基礎(chǔ)

第1章   導(dǎo)論                  
 11數(shù)制的簡單回顧                  
 111 八進(jìn)制數(shù)和十六進(jìn)制數(shù)                  
 112 二進(jìn)制加法                  
 113 有符號數(shù)                  
 114 二進(jìn)制減法                  
 115 二十進(jìn)制碼（BCD）                  
 12 組合系統(tǒng)的設(shè)計(jì)過程                  
 13 列真值表                  
 14 無關(guān)條件                  
 15 實(shí)驗(yàn)室                  
 16 解題實(shí)例                   
                   
  第2章 開關(guān)代數(shù)和邏輯電路                   
 21 開關(guān)代數(shù)的定義                  
 22 開關(guān)代數(shù)的基本性質(zhì)                  
 23 代數(shù)函數(shù)的處理                  
 24 用與門. 或門和非門實(shí)現(xiàn)邏輯函數(shù)                  
 25 從真值表到代數(shù)表達(dá)式                   
 26 卡諾圖初步                  
 27 補(bǔ)和或與                  
 28 與非門. 或非門和異或門                  
 29 代數(shù)表達(dá)式的化簡                  
 210 代數(shù)函數(shù)的處理及其與非門實(shí)現(xiàn)                  
 211 布爾代數(shù)                  
 212 解題實(shí)例                  
 213 習(xí)題                   
                   
                   
                   
  第3章 兩種規(guī)范性的化簡方法                   
 3.1  卡諾圖                  
  3.1.1 用卡諾圖求解最簡與或表達(dá)式                  
  3.1.2 無關(guān)項(xiàng)                  
  3.1.3 或與式                  
  3.1.4 最省門的電路實(shí)現(xiàn)                  
  3.1.5 五變量和六變量的卡諾圖                  
  3.1.6 多輸出問題                  
 3.2  規(guī)律性的最簡化方法                  
 3.2.1 單輸出的迭代合意                  
 3.2.2 單輸出的質(zhì)蘊(yùn)含項(xiàng)表                  
 3.2.3 多輸出問題的迭代合意                  
 3.3 解題實(shí)例                  
 3.4 習(xí)題                   
                   
 第4章 較大規(guī)模的系統(tǒng)設(shè)計(jì)                   
                   
 4.1 組合邏輯電路中的延時                  
 4.2 加法器                  
 4.3 譯碼器                  
 4.4 編碼器和優(yōu)先權(quán)編碼器                  
 4.5 數(shù)據(jù)選擇器                  
 4.6 三態(tài)門                  
 4.7  門陣列--ROM, PLA和PAL                  
 4.7.1 用只讀存儲器進(jìn)行設(shè)計(jì)                  
 4.7.2 用可編程邏輯陣列進(jìn)行設(shè)計(jì)                  
 4.7.3 用可編程陣列邏輯進(jìn)行設(shè)計(jì)                  
 4.8  較大規(guī)模電路的例子                  
 4.8.1 七段顯示                  
 4.8.2 差錯編碼和解碼系統(tǒng)                  
 4.9 解題實(shí)例                  
 4.10 習(xí)題                   
  第5章 時序系統(tǒng)                   
 5.1 閂鎖和觸發(fā)器                   
 5.2 同步時序系統(tǒng)的設(shè)計(jì)過程                  
 5.3 時序系統(tǒng)的分析                  
 5.4 觸發(fā)器的設(shè)計(jì)方法                  
 5.5 同步計(jì)數(shù)器的設(shè)計(jì)                  
 5.6 異步計(jì)數(shù)器的設(shè)計(jì)                  
 5.7 生成狀態(tài)表和狀態(tài)圖                  
 5.8 解題實(shí)例                  
 5.9 習(xí)題                   
                   
  第6章 求解較大規(guī)模的時序問題                   
 6.1 移位寄存器                  
 6.2 計(jì)數(shù)器                  
 6.3 可編程邏輯器件（PLD）                  
 6.4 用ASM圖進(jìn)行設(shè)計(jì)                  
 6.5 硬件設(shè)計(jì)語言（HDL）                  
 6.6 更復(fù)雜的例子                  
 6.7 解題實(shí)例                  
 6.8 習(xí)題                   
                   
  第7章 時序電路化簡                   
 7.1 列表法進(jìn)行狀態(tài)化簡                  
 7.2  分割法                  
 7.2.1 分割的性質(zhì)                  
 7.2.2 求SP分割                  
 7.3 用分割法進(jìn)行狀態(tài)化簡                  
 7.4 選擇狀態(tài)分配                  
 7.5 解題實(shí)例                  
 7.6 習(xí)題                   
  附錄A 實(shí)驗(yàn)